1. Field of the Invention
This invention relates to EEPROM devices and more particularly to bit erasing as well as block erasing therein.
2. Description of Related Art
In the past in EEPROM devices, erasure has been performed groups of eight bits known as a byte, byte by byte, but one cell needs 2 1/8 transistors and tunneling window, so the cell size is large. See FIG. 1B where a cell includes a cell transistor Tc, a bit select transistor T.sub.bit, and share the byte select transistor T.sub.byte with seven other cells.
An alternative to the EEPROM which solves part of the problem of large cell size is the flash EPROM. While the flash EPROM has the advantage that the cell size is small, the problem is that the flash EPROM has the disadvantage that it erases block by block, and one can not use it to erase bit by bit or byte by byte.
FIG. 1A shows a cross section of a prior art device known as a FLOTOX (Floating-Gate Tunneling Oxide) EEPROM cell known as an E.sup.2 PROM cell which requires a tunnel oxide window and a select transistor, not shown in FIG. 1A, so the cell size is large. The FLOTOX cell is described in Samachisa et al of SEEQ Technology Inc. and U of C, Berkeley for "A 128 k Flash EEPROM Using Double-Polysilicon Technology" IEEE J Solid-State Circuits Vol SC-22, No. 5, pp 676-683 (October 1987.) In FIG. 1A the device includes a P-substrate 10 containing a drain region 11 connected to V.sub.d voltage source, a source region 12 connected to V.sub.s voltage source, a tunnel oxide 14, gate oxide layer 15, a field oxide (FOX) 16, a floating gate 17 composed of polysilicon 1 first dielectric layer 18, a control gate 19 composed of polysilicon 2 connected to V.sub.g voltage source, and a second dielectric layer 20. The tunnel oxide 14 is located between the floating gate 17 and the N+ drain region 12.
FIG. 1B shows a prior art E.sup.2 PROM cell array (in accordance with FIG. 1A) and shows the connection lines required for its operation. Referring to Table 1 an operation table shows how an E.sup.2 PROM can program and erase in groups of cells, by the byte (8 bits.)
TABLE 1 ______________________________________ PROGRAM ERASE READ ______________________________________ SELECTED WORD LINE 20 V 20 V 5 V UNSELECTED WORD LINE 0 V 0 V 0 V PROGRAM LINE 17 V 0 V 0 V BIT LINE 0 (ERASED) 0 V 17 V 1.6 V BIT LINE 7 (PROGRAMMED) 0 V 0 V 2.0 V ______________________________________
FIG. 2A shows a prior art flash memory cell structure know as an ETOX.RTM. flash memory comprising a flash memory cell with tunnel oxide TO below the floating gate FG. The device includes source S and drain D in the substrate and a control gate CG above the floating gate FG separated therefrom by a dielectric layer, with the erase E function from floating gate FG to source indicted and the programming P function from drain to floating gate FG indicated.
FIG. 2B shows a cell array of the prior art device of FIG. 2A. The array is controlled by bit lines BL1, BL2, BL3 and BL4 which extend vertically to the cells. The bit lines are connected to the S/D circuits of the cells, which are connected at the opposite ends to one of a plurality of voltage supply sources represented by V.sub.ss1, V.sub.ss2, and V.sub.ss3. Word lines WL1, WL2, and WL3 are the horizontally directed lines connected to the cells. In particular, the word lines WL1, WL2, and WL3 are connected to the control gates of the cells. FIG. 2B along with TABLE 2 which is a flash memory operation table shows how such an ETOX flash memory device operates. In particular, Table 2 below shows the operation table for the ETOX flash memory of FIGS. 2A and 2B is unable to program and erase by byte (8 bits.) Referring to Table 2, one can program or read a single bit (cell,) but one can not erase a single bit, because the word lines WL1, WL2, . . . WLn and V.sub.ss1, V.sub.ss2 . . . V.sub.ssn lines are parallel with each other (i.e. are oriented in the same direction.)
TABLE 2 ______________________________________ PROGRAM ERASE READ ______________________________________ SELECTED WORD LINE (WL2) 12 V 0 V 5 V UNSELECTED WORD LINE 0 V 0 V 0 V (WL1, WL3) SELECTED BIT LINE (2) 7 V 0 V 1.6 V UNSELECTED BIT LINE 1, 3, 4 0 V 0 V 0 V SELECTED V.sub.SS 0 V) 12 V 0 V UNSELECTED V.sub.SS (1, 3) 0 V 0 V 0 V ______________________________________